`include "defines.v"

module ex_mem(
    input wire clk,
    input wire rst,

    //from ex module
    input wire[`MemAddrBus] addr_i,
    input wire[`MemBus] wdata_i,
    input wire we_i,
    // to ex
    output reg[`MemBus] rdata_o
);


    reg[`MemBus] _ram[0:`MemNum - 1];
        
        initial begin
        $readmemb("data_ram.mem",_ram);
        end

    
    always @ (posedge clk) begin
            if (rst == `RstDisable && we_i == `WriteEnable) begin
                _ram[addr_i[31:2]] <= wdata_i;
            end
        end

    always @ (*) begin 
        if (rst == `RstEnable)
            rdata_o = `ZeroWord;
        else 
            rdata_o = _ram[addr_i[31:2]];
    end
endmodule